Proficient matrix codes for error detection and correctionin 8-port network on chip routers

This paper verifies the applicability of proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism adaptive routing algorithm bypasses components dynamically and router architecture uses additional diagonal state indications for reliable network chip (NoC) operation. In NoC, permanently routers are disconnected enable high throughput as data packets not lost due self-loopback mechanism. The proficient matrix codes use capabilities decimal technique minimum check bits maximum correction capability. is compared existing such codes, modified parity codes. developed in verilog hardware description language simulated Xilinx ISE 14.5 tool. proves be efficient multiple adjacent trade off delay. Also 65% rate achieved 22.73% less redundant occupy area by atleast 11.78%. when used increased sizes like 8, 16, 32, 64 bits, power delay product decreased 1.74%.